Understanding large swing and low swing operation in DyCML gates

This paper investigates the operation of dynamic current-mode logic gates (DyCML), under large swing and low swing conditions. Traditionally, the operation of DyCML gates is ruled by charge distribution models, stating that, the output charge is transferred during the evaluation phase to a dynamic current source capacitor. Output swing is governed by the ratio between load and dynamic source capacitances, which are able to accommodate all the output voltage swing. This paper shows that this model is not adequate for all output swing conditions; in particular there are two different modes that need to be considered. Simulation results, using a standard 350nm CMOS process provide evidence of these different behaviors. Second order effects are also considered, providing guidelines for future research.