A process-compatible passive RFID tag´s digital design for subthreshold operation

Based on deep submicron CMOS technologies and limit power availability, a low-power subthreshold passive UHF RFID tag´s digital design is presented in this paper. The design uses specific techniques for ultra-low-voltage condition, addressing the long logic propagation time and wide-range-variation problems. According to the EPC C1G2 protocol, compensated addition is proposed in PIE decoding, and power-aware scheme is applied to the entire architecture. Additionally, double-edge-triggered technique helps to improve clock efficiency, reducing the complexity and power of the tag´s clock generator. Galoi linear feedback shift register (LFSR) and one-hot counter are applied to meet the critical timing requirements in command handling blocks. To ensure the compatibility, the baseband processor was fabricated in 180nm, 130nm and 90nm CMOS technologies respectively, and the logic designs indicate good robustness in very-low supply voltage testing. Minimum operating voltages are at least 70 mV lower than the regular threshold voltage.