A 11b 5.1µW multi-slope ADC with a TDC using multi-phase clock signals

We propose a multi-slope ADC with a Time to Digital Converter (TDC). In a single-slope ADC, when using a TDC that has resolution of n bits, the conversion time will be reduced by a factor of 2ⁿ. Applying the TDC that uses the multi-phase-clock signal reduced the circuit areas of TDC by half, achieved timing consistency, and realized robust meta-stability. We also apply multi-slope scheme for reducing the ADC-operation cycles. We designed and fabricated an 11-bit ADC, by using a TSMC 0.18-μm CMOS process. The ADC, at 100 kS/s, achieved SNDR of 59.6 dB (9.6 ENOB) and SFDR of 72.7 dB. Its INL and DNL were +1.32/-0.80LSB and +0.48/-0.37LSB, respectively. The entire ADC consumes 5.1μW from a 1-V supply.