DocumentCode
596975
Title
Design of hybrid resistive-capacitive DAC for SAR A/D converters
Author
Sedighi, Behnam ; Huynh, A.T. ; Skafidas, E. ; Micusik, D.
Author_Institution
Dept. Electr. & Electron. Eng., Univ. of Melbourne, Parkville, VIC, Australia
fYear
2012
fDate
9-12 Dec. 2012
Firstpage
508
Lastpage
511
Abstract
While hybrid capacitive-resistive D/A Converter (DAC) has been known for many years, its potential for energy-efficient operation is sometimes overlooked. This paper investigates the utilization of hybrid DACs in successive-approximation register A/D converters. To improve energy efficiency of SAR ADCs, a new hybrid DAC is introduced. In an exemplar 10-bit 100-MS/s ADC, simulation results show that the energy efficiency and chip area (of passive devices) can be improved by more than an order of magnitude.
Keywords
analogue-digital conversion; digital-analogue conversion; energy conservation; logic design; SAR A-D converters; SAR ADC energy efficiency; chip area; energy-efficient operation; hybrid resistive-capacitive DAC design; storage capacity 10 bit; successive-approximation register A-D converters; Capacitance; Capacitors; Energy efficiency; Noise; Power dissipation; Resistors; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on
Conference_Location
Seville
Print_ISBN
978-1-4673-1261-5
Electronic_ISBN
978-1-4673-1259-2
Type
conf
DOI
10.1109/ICECS.2012.6463697
Filename
6463697
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