A 4-bit 1.5GSps 4.2mW comparator-based binary search ADC in 90nm

Traditional ADC architectures often fail to provide the required balance between low-power and high sampling rate, leaving room for further topology exploration. We propose a modified binary search ADC topology, which relies on a pipeline for the comparator stages and tracks the input in a time-interleaved fashion. Extensive statistical simulations for the 4-bit proposed ADC show that, sampling at 1.5GSps, the ADC consumes 4.2mW, providing 3.67 effective bits and a figure of merit of 219fJ/conversion step, without requiring calibration.