Ultra-low voltage drain-bulk connected MOS transistors in weak and moderate inversion

Author

Dimakos, Athanasios ; Bucher, Matthias ; Sharma, Ratnesh K. ; Chlis, Ilias

Author_Institution

Dept. of Electron. & Comput. Eng., Tech. Univ. of Crete, Chania, Greece

fYear

2012

fDate

9-12 Dec. 2012

Firstpage

17

Lastpage

20

Abstract

This paper aims to demonstrate the basic characteristics of NMOS and PMOS drain-bulk connected transistors for ultra-low voltage applications. On-wafer measurements were done on 180nm CMOS process, while TCAD simulations were done for 180nm and 45nm technology nodes. Analytical expressions for Early voltage and intrinsic gain in weak-moderate inversion are provided, showing that these quantities are dominated by the substrate effect and are insensitive to bias and geometry. Furthermore, the analytical model as well as the EKV3 MOSFET compact model, following suitable parameter extraction, show a close agreement to measured and TCAD simulated data.

Keywords

CMOS analogue integrated circuits; MOSFET; low-power electronics; semiconductor device models; technology CAD (electronics); CMOS process; EKV3 MOSFET compact model; NMOS drain-bulk connected transistors; PMOS drain-bulk connected transistors; TCAD simulations; on-wafer measurements; size 180 nm; size 45 nm; substrate effect; ultralow-voltage drain-bulk connected MOS transistors; weak-moderate inversion; Analytical models; Data models; Integrated circuits; MOSFETs; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on

Conference_Location

Seville

Print_ISBN

978-1-4673-1261-5

Electronic_ISBN

978-1-4673-1259-2

Type

conf

DOI

10.1109/ICECS.2012.6463711

Filename

6463711