Title :
Maximum delay variation temperature-aware standard cell design
Author :
Pons, Marc ; Nagel, J. ; Piguet, Christian
Abstract :
Standard cell design suffers from temperature-induced delay uncertainty. In this paper we propose two methodologies to cope with this issue before the logic synthesis step without modifying the standard flow. Both methodologies are based on the study of the cell maximum delay sensitivity to temperature variations to select the cells of the library to be used for the synthesis. We provide icyflex2 CSEM processor synthesis to demonstrate the delay variability reduction obtained.
Keywords :
logic design; cell maximum delay sensitivity; delay variability reduction; icyflex2 CSEM processor synthesis; logic synthesis; maximum delay variation temperature-aware standard cell design; temperature variations; temperature-induced delay uncertainty; Delay; Equations; Libraries; Sensitivity; Standards; Temperature measurement; Temperature sensors;
Conference_Titel :
Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on
Conference_Location :
Seville
Print_ISBN :
978-1-4673-1261-5
Electronic_ISBN :
978-1-4673-1259-2
DOI :
10.1109/ICECS.2012.6463743
