A power efficient 3-Gbits/s 1.8V PMOS-based LVDS output driver

Author

Marar, Hazem W. ; Abugharbieh, Khaldoon ; Al-Tamimi, Abdel-Karim

Author_Institution

Electron. Eng. Dept., Princess Sumaya Univ. for Technol., Amman, Jordan

fYear

2012

fDate

9-12 Dec. 2012

Firstpage

240

Lastpage

243

Abstract

This paper presents a new topology of a PMOS based LVDS voltage-mode output driver. This topology is designed to meet the requirements of low power consumption and high data rates applications. The driver, which consists of a pre-driver stage and an output stage, uses a positive feedback technique at the output stage to achieve line impedance matching and power saving. The pre-driver stage is used to set the driver´s swing and common mode output voltage. The pre-driver and the output stage consume only 9mW of power at 3 Gbps speed while operating from a 1.8V voltage supply. The system is designed and simulated using CMOS 180nm technology and is fully compliant with LVDS output swing and common mode voltage specifications.

Keywords

CMOS integrated circuits; driver circuits; low-power electronics; telecommunication signalling; CMOS technology; LVDS output driver; bit rate 3 Gbit/s; high data rate application; line impedance matching; low power consumption application; low voltage differential signaling; output stage; positive feedback technique; power 9 mW; power efficient PMOS; power saving; predriver stage; size 180 nm; voltage 1.8 V; voltage mode output driver; CMOS integrated circuits; CMOS technology; Mathematical model; Resistance; Resistors; Standards; Topology; LVDS; PMOS-based; high speed data rate communication circuits; low power; low-voltage; output drivers; voltage mode;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on

Conference_Location

Seville

Print_ISBN

978-1-4673-1261-5

Electronic_ISBN

978-1-4673-1259-2

Type

conf

DOI

10.1109/ICECS.2012.6463756

Filename

6463756