Analysis of ESD protection circuits for high — Performance CMOS structures

Author

Nicuta, A. ; Beniuga, O.C. ; Bicleanu, P.D. ; Bargan, L.

Author_Institution

Gheorghe Asachi Tech. Univ. of Iasi, Iasi, Romania

fYear

2012

fDate

25-27 Oct. 2012

Firstpage

713

Lastpage

716

Abstract

Due to the low breakdown voltage of the gate oxide in CM OS technologies, highly effective Electrostatic Discharge (ESD) protection designs should be implemented in each device technology. Therefore, innovative protection designs were investigated in order to increase the high - precision and robustness of the integrated CMOS structures. The paper aims to create the context in which the proposed designs achieve an effective protection by reducing the high-currents, when ESD voltage pulses of fast rise time are applied at the inputs of the circuits.

Keywords

CMOS integrated circuits; electric breakdown; electrostatic discharge; integrated circuit design; ESD protection circuit analysis; ESD voltage pulse; electrostatic discharge; gate oxide; high-performance CMOS structure technology; voltage breakdown; Biological system modeling; CMOS integrated circuits; CMOS technology; Discharges (electric); Electrostatic discharges; Integrated circuit modeling; Logic gates; CMOS structures; Electrostatic Discharge (ESD); protection circuits design;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Power Engineering (EPE), 2012 International Conference and Exposition on

Conference_Location

Iasi

Print_ISBN

978-1-4673-1173-1

Type

conf

DOI

10.1109/ICEPE.2012.6463847

Filename

6463847