Cell design and comparative evaluation of a novel 1T memristor-based memory

CMOS is expected to soon meet the end of the Semiconductor Industry Technology Roadmap. This paper investigates the memristor as a post-CMOS component for memory design. The proposed cell requires one transistor and one memristor (i.e. 1T1M); this cell employs novel read and write mechanisms for improved performance. Initially, it is shown that differently from previous designs, the proposed scheme accomplishes a read operation that does not affect the memory state; this cell is assessed with respect to different parameters as related to its design (such as applied write voltage, memristor range and size). It is shown that at array-level, the write operation may still incur in a state change due to voltage degradation. A detailed assessment of the relationship between a linear array size (as dimension of a square memory array) and the cell parameters, is pursued. Moreover, a comparison with a DRAM cell (i.e. 1T1C) in CMOS is pursued; the advantages and disadvantages of DRAM versus memristor based arrays are then presented.