• DocumentCode
    597229
  • Title

    ToPoliNano: Nanoarchitectures design made real

  • Author

    Frache, Stefano ; Chiabrando, Diego ; Graziano, Mariagrazia ; Riente, Fabrizio ; Turvani, Giovanna ; Zamboni, Maurizio

  • Author_Institution
    Electron. & Telecommun. Dept., Politec. di Torino, Turin, Italy
  • fYear
    2012
  • fDate
    4-6 July 2012
  • Firstpage
    160
  • Lastpage
    167
  • Abstract
    Many facts about emerging nanotechnologies are yet to be assessed. There are still major concerns, for instance, about maximum achievable device density, or about which architecture is best fit for a specific application. Growing complexity requires taking into account many aspects of technology, application and architecture at the same time. Researchers face problems that are not new per se, but are now subject to very different constraints, that need to be captured by design tools. Among the emerging nanotechnologies, two-dimensional nanowire based arrays represent promising nanostructures, especially for massively parallel computing architectures. Few attempts have been done, aimed at giving the possibility to explore architectural solutions, deriving information from extensive and reliable nanoarray characterization. Moreover, in the nanotechnology arena there is still not a clear winner, so it is important to be able to target different technologies, not to miss the next big thing. We present a tool, ToPoliNano, that enables such a multi-technological characterization in terms of logic behavior, power and timing performance, area and layout constraints, on the basis of specific technological and topological descriptions. This tool can aid the design process, beside providing a comprehensive simulation framework for DC and timing simulations, and detailed power analysis. Design and simulation results will be shown for nanoarray-based circuits. ToPoliNano is the first real design tool that tackles the top down design of a circuit based on emerging technologies.
  • Keywords
    electronic engineering computing; integrated circuit layout; nanotechnology; DC simulation; ToPoliNano tool; circuit top down design; design process; layout constraint; logic behavior; massively parallel computing architecture; multitechnological characterization; nanoarchitecture design; power performance; reliable nanoarray characterization; timing performance; timing simulation; two dimensional nanowire based arrays; Computer architecture; Fabrics; Integrated circuit modeling; Layout; Nanoscale devices; Routing; Tiles;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nanoscale Architectures (NANOARCH), 2012 IEEE/ACM International Symposium on
  • Conference_Location
    Amsterdam
  • Print_ISBN
    978-1-4503-1671-2
  • Type

    conf

  • Filename
    6464158