A study on gate-AU-around (GAA) polycrystalline silicon channel SONOS flash memory

Author

Joo Yun Seo ; Sang-Ho Lee ; Yoon Kim ; Se Hwan Park ; Wandong Kim ; Do-Bin Kim ; Byung-Gook Park

Author_Institution

Inter-Univ. Semicond. Res. Center (ISRC), Seoul Nat. Univ., Seoul, South Korea

fYear

2013

fDate

2-4 Jan. 2013

Firstpage

69

Lastpage

71

Abstract

In this study, the gate-all-around (GAA) poly-Si channel flash memories with charge trap layer (Si₃N₄) have been successfully fabricated. Electric characteristics of fabricated devices including threshold voltage shift with program/erase operation have been investigated. Gate configurations were structured differently according to each defined channel width. Results show that devices with gate-all-around structure have superior program efficiency. To investigate the effect of gate configuration on the program efficiency, TCAD simulation was carried out.

Keywords

flash memories; silicon compounds; technology CAD (electronics); GAA polycrystalline silicon channel SONOS flash memory; Si₃N₄; TCAD simulation; electric characteristics; gate configuration; gate-AU-around polycrystalline silicon channel SONOS flash memory; gate-all-around structure; program-erase operation; Conferences; Decision support systems; Nanoelectronics; SONOS flash memory; charge trap memory; gate-all-around (GAA);

fLanguage

English

Publisher

ieee

Conference_Titel

Nanoelectronics Conference (INEC), 2013 IEEE 5th International

Conference_Location

Singapore

ISSN

2159-3523

Print_ISBN

978-1-4673-4840-9

Electronic_ISBN

2159-3523

Type

conf

DOI

10.1109/INEC.2013.6465956

Filename

6465956