Title :
FinFET device Capacitances: Impact of input transition time and output load
Author :
Pandey, Ashutosh ; Raycha, Swati ; Maheshwaram, Satish ; Manhas, Sanjeev Kumar ; Dasgupta, S. ; Saxena, Alok Kumar ; Anand, B.
Author_Institution :
Dept. of Electron. & Comput. Eng., Indian Inst. of Technol. Roorkee, Roorkee, India
Abstract :
FinFET devices with source drain underlaps are attractive due to their high Ion/Ioff ratios [1]. However, a thorough understanding of the device parasitics on underlap FinFET circuit performance is yet to be attained. In this paper, we report a new Extension Transistor Induced Capacitance Shielding (ETICS) phenomenon. Due to this phenomenon, the effective values of a FinFET logic gate´s input and parasitic capacitances depend strongly on transition times of its terminal voltages. We show that understanding of this phenomenon is essential for circuit design.
Keywords :
MOSFET; logic gates; ETICS phenomenon; FinFET device capacitances; circuit design; extension transistor induced capacitance shielding phenomenon; input transition time; logic gate; output load; parasitic capacitances; source drain; terminal voltages; Capacitance; Circuit optimization; Equivalent circuits; FinFETs; Inverters; Logic gates; Underlap FinFET; capacitance shielding and inverter delay; parasitic capacitance; three transistor equivalent circuit;
Conference_Titel :
Nanoelectronics Conference (INEC), 2013 IEEE 5th International
Conference_Location :
Singapore
Print_ISBN :
978-1-4673-4840-9
Electronic_ISBN :
2159-3523
DOI :
10.1109/INEC.2013.6466050
