Title :
Physical/process parameter dependence of gate capacitance and ballistic performance of InAsySb1−y Quantum Well Field Effect Transistors
Author :
Niaz, I.A. ; Alam, Md Hasibul ; Ahmed, Ishtiaq ; Al Azim, Zubair ; Chowdhury, Nasirul ; Khosru, Quazi D. M.
Author_Institution :
Dept. of Electr. & Electron. Eng., Bangladesh Univ. of Eng. & Technol., Dhaka, Bangladesh
Abstract :
This paper reports complete Capacitance-Voltage (CV) characterization of InAsySb1-y Quantum Well Field Effect Transistor (QWFET) along with an analysis of ballistic transport performance. 1-D coupled Schrodinger-Poisson equations are solved for electrostatic performance analysis of QWFET considering wave function penetration and strain effects. Dependence of CV characteristics on some important process and physical parameters like oxide thickness, channel composition, top barrier composition, channel thickness and temperature is studied in this work. We observed that before cross-over point the capacitance increases rapidly and gradually reaches saturation after that point. This is because the slope of the sheet charge density gradually increases and finally reaches almost a constant value. The pattern of variation of simulation results are consistent with the results of experimentally grown device by Ali et al. Ballistic current is also reported to improve from compressive to tensile strained channel.
Keywords :
III-V semiconductors; MOSFET; Poisson equation; Schrodinger equation; ballistic transport; capacitance; indium compounds; quantum well devices; semiconductor quantum wells; 1D coupled Schrodinger-Poisson equations; InAsySb1-y; QWFET; ballistic current; ballistic transport performance; complete CV characterization; complete capacitance-voltage characterization; constant value; electrostatic performance analysis; gate capacitance; physical parameters; process parameter dependence; quantum well field effect transistors; sheet charge density; strain effects; tensile strained channel; wave function penetration; Capacitance; Charge carrier density; Dielectrics; Logic gates; Mathematical model; Strain; Temperature; Buried channel device; high k dielectric; quantum well FET; strain and wave function penetration;
Conference_Titel :
Nanoelectronics Conference (INEC), 2013 IEEE 5th International
Conference_Location :
Singapore
Print_ISBN :
978-1-4673-4840-9
Electronic_ISBN :
2159-3523
DOI :
10.1109/INEC.2013.6466055