Design and analysis of high speed shift register using Single clock pulse method

Today´s electronic devices move drastically towards high speed design feature. The traditional D-flip flop is no longer suitable for designing shift registers because of its low-speed performance. Many different types of shift registers, such as Universal Shift registers, Serial In Serial Out, Serial In Parallel Out, Parallel In Parallel Out and Parallel In Serial Out have been developed. Also, there are many low-power shift register design techniques that have been proposed. However, they are all lagging behind in high speed performances. The shift register design using Single clock pulse with Hold Mode (HM-FF) & without Hold Mode (WHM-FF) Flip Flop can be a potential solution to this problem. The shift register design using this proposed method promises to achieve tremendous improvements in performance of speed. When compared to its conventional counterparts, the proposed design is able to attain more than 41.9% reduction in over all time delay, which is targeted to Xilinx Virtex 6 devices.