Title :
Achieveing reduced area by Multi-bit Flip flop design
Author :
Prakash, Gl ; Sathishkumar, K. ; Sakthibharathi, B. ; Saravanan, S. ; Vijaysai, R.
Author_Institution :
VLSI Design, SASTRA Univ., Thanjavur, India
Abstract :
Timing Optimization is one of the most important objectives of the designer in the Modern VLSI world. Memory elements play a vital role on Digital World. The basic memory elements of designer considerations are Latch and flip flop. In this paper, we analyze the design of Single-bit Flipflop (SBFF) and made performance comparison over the Multi-bit Flip-flop (MBFF). For improving Flip flop performance one of the promising way is to merge the clock pulse. The Multi-bit Flip-flop is designed by single clock pulse and achieves same functionality like two single-bit Flip-flop. A shift register is designed using both Single-Bit Flip-Flop (SBFF) and Multi-Bit Flip-Flop (MBFF). This paper analyzes the timing performance of both SBFF and MBFF in Xilinx Virtex-5 family (XC5VLX50). These results in favor of Multi-Bit Flip-Flop as reduction of Clock network such as clock buffer and gate delay.
Keywords :
VLSI; buffer circuits; clocks; field programmable gate arrays; flip-flops; integrated circuit design; logic design; logic gates; performance evaluation; MBFF; SBFF; VLSI world; XC5VLX50; Xilinx Virtex-5 family; clock buffer; clock network reduction; clock pulse; digital world; flip flop performance improvement; gate delay; latch; memory elements; multibit flip flop design; reduced area achievement; single-bit flipflop design; timing optimization; Clocks; Delay; Flip-flops; Latches; Logic gates; Optimization; Clock buffer; Clock network; Flip-flop; Gate delay; Latch; Multi bit flip flop; Single bit flip flop;
Conference_Titel :
Computer Communication and Informatics (ICCCI), 2013 International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4673-2906-4
DOI :
10.1109/ICCCI.2013.6466259
