Design of low power clocking system using merged flip-flop technique

The clock power is the major dynamic power source in sequential VLSI circuits. In order to reduce this power a lots of techniques are available. One of them is the use of multi-bit flip-flop. In this technique the power consumption is reduced by replacing some flip-flop with multi-bit flip-flops. This may cause some performance degradation to the original circuit. To avoid the performance degradation the flip-flops that are going to merge must satisfy certain timing constraint. The concept of combination table is introduced in the proposed work. The combination table contains the flip-flops that can be merged. According to the experimental results it is found that the flipflops after merging reduces the dynamic power about 23.68% and the total power about 8.55%. It is also found that the global clock buffer is reduced to 37.84%.