A 1.25/2.5/3.125Gbps CDR circuit with a phase interpolator for RapidIO application

Author

Hailing Yang ; Yuan Wang ; Song Jia ; Ganggang Zhang ; Xing Zhang

Author_Institution

Key Lab. of Microelectron. Devices & Circuits (MoE), Peking Univ., Beijing, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

A phase interpolator (PI)-based clock data recovery (CDR) circuit for RapidIO application is presented, which avoids the coupled interference of VCOs. With the integration of a digital control cell, the complex and area consumption has been reduced effectively. An adaptive bandwidth PLL structure is adopted so that it can provide clocks of three frequencies while maintain a good jitter performance. In a 0.13um CMOS process, the circuit has a jitter of 11.2ps@3.125Gbps with a power consumption of 21.7mW under 1.2V, and the core circuit area is 0.16mm².

Keywords

CMOS digital integrated circuits; clocks; integrated circuit interconnections; phase locked loops; synchronisation; voltage-controlled oscillators; CDR circuit; CMOS process; RapidIO application; VCO; adaptive bandwidth PLL structure; bit rate 1.25 Gbit/s; bit rate 2.5 Gbit/s; bit rate 3.125 Gbit/s; clock data recovery circuit; coupled interference; digital control cell; phase interpolator; power 21.7 mW; size 0.13 mum; voltage 1.2 V; Clocks; Computer architecture; Digital control; Jitter; Microprocessors; Phase locked loops; Simulation; adaptive bandwidth PLL; clock and data recovery; current mode logic; phase interpolator;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6466691

Filename

6466691