A low power PLL quadrature frequency synthesizer for Zigbee applications

Author

Xiaodong Liu ; Wenfeng Lou ; Haiyong Wang ; Nanjian Wu

Author_Institution

State Key Lab. for Super Lattices & Microstructures, Inst. of Semicond., Beijing, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

A low power PLL quadrature frequency synthesizer for Zigbee applications is presented. The current reusing and forward-body bias techniques are applied to decrease power consumption and to improve noise characteristic of the synthesizer. The synthesizer is implemented in 0.18μm CMOS process and the core chip area is about 1.2×1.2mm². Measured results show that the frequency tuning range is 2.04-2.49GHz and the locking time is less than 75μs. The phase noises are -110.4dBc/Hz and -125.5dBc/Hz at the offset of 1MHz and 10MHz, respectively. The reference spur is -68.45dBc at the offset of 2.5MHz. It consumes only 3.2mA current at a 1.8V operating voltage.

Keywords

CMOS integrated circuits; Zigbee; frequency synthesizers; low-power electronics; phase locked loops; CMOS process; Zigbee application; core chip area; current 3.2 mA; decrease power consumption; forward body bias technique; frequency 1 MHz; frequency 10 MHz; frequency 2.04 GHz to 2.49 GHz; frequency 2.5 MHz; frequency tuning range; low power PLL quadrature frequency synthesizer; noise characteristic; size 0.18 mum; voltage 1.8 V; Frequency synthesizers; Phase locked loops; Phase noise; Power demand; Semiconductor device measurement; Synthesizers; Zigbee;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6466716

Filename

6466716