A low-jitter low-area PLL with process-independent bandwidth

The noise performance of PLL(Phase-Locked Loop) is closely related to the loop bandwidth. Unfortunately, process variation would influence I_CP (charge pump current) and K_VCO (gain of Voltage-Controlled-Oscillator), and then keep the PLL bandwidth sufficiently far away from the designed value. In this paper, a Digital Auxiliary Method (DAM) is proposed to reduce the change on I_CP and K_VCO due to process variation and stabilize the loop bandwidth. The PLL design is based on 0.18μm CMOS technology with a 1.8V power supply. Measurement results show that both of the variations are able to be compensated by the Digital Auxiliary Method and keep the bandwidth stable. Depending on the DAM, the output frequency of PLL is 200.68MHz which is 0.34% away from the designed value. The peak-to-peak jitter and rms jitter are 150.2ps and 30.6ps separately.