Si Nanowire tunnel FETs with epitaxial NiSi2 source/drain and dopant segregation

Si Nanowire (NW) TFETs with a NW cross section of 30×7nm² were fabricated on ultra thin SOI. Implanattion into epitaxial NiSi₂ silicide (IIS) source and drain and a subsequent anneal at low temperatures for dopant segregation (DS) were used for formation of junctions. Si NW Schottky MOSFETs with dopant segregated NiSi₂ source/drain showed very low Schottly barrier, which demonstrates a high concentration of dopants segregated at the NiSi₂ edges even after low temperature anneals. Tilted dopant implantation using the gate as a shadow mask allows self-aligned formation of p-i-n tunneling FETs. The steep junctions fromed at low temperature improve the band-to-band tunneling. P-channel TFETs showed high on-currents (I_ON) of 18.8 μA/μm, very low off-currents (I_OFF) and a large I_ON/I_OFF ratio up to 10⁸.