DocumentCode
597843
Title
Exploration of a reconfigurable 2D mesh network-on-chip architecture and a topology reconfiguration algorithm
Author
Zi-Xu Wu ; Jin-Xiang Wang ; Ji-Yuan Zhang ; Xiao-Yu Wang ; Fang-Fa Fu
Author_Institution
Micro-Electron. Center, Harbin Inst. of Technol., Harbin, China
fYear
2012
fDate
Oct. 29 2012-Nov. 1 2012
Firstpage
1
Lastpage
3
Abstract
A novel reconfigurable 2D mesh Network-on-Chip (NoC) architecture (REmesh) and a topology reconfiguration algorithm (TRARE) are proposed in this paper. Compared with a conventional 2D mesh, REmesh, which employs a few more routers and multiplexers, can be easily reconfigured to restore a 2D mesh topology to tolerant core faults in NoCs. Based on REmesh, TRARE repeatedly categorizes routers, connects cores with routers, and eventually finds out a reconfiguration solution. Simulation results show that in the topologies which sizes do not exceed 7×8, more than 90% successful reconfiguration rate can be guaranteed when less than 9% of the total cores are faulty. Simulation also suggests that when the number of faulty cores reaches the number of redundant cores, more redundancy should be added to ensure high successful reconfiguration rate.
Keywords
fault tolerance; mesh generation; multiplexing equipment; network routing; network-on-chip; reconfigurable architectures; topology; 2D mesh topology; NoC architecture; REmesh; TRARE; multiplexer; reconfigurable 2D mesh network-on-chip architecture; reconfiguration rate; redundant core; router; tolerant core fault; topology reconfiguration algorithm; Approximation algorithms; Circuit faults; Computer architecture; Multiplexing; Network topology; Redundancy; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location
Xi´an
Print_ISBN
978-1-4673-2474-8
Type
conf
DOI
10.1109/ICSICT.2012.6466732
Filename
6466732
Link To Document