Time divided architecture for closed loop MEMS capacitive accelerometer

Author

Jingqing Huang ; Tingting Zhang ; Meng Zhao ; Lichen Hong ; Yacong Zhang ; Wengao Lu ; Zhongjian Chen ; Yilong Hao

Author_Institution

Dept. of Microelectron., Peking Univ., Beijing, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

This paper mainly discusses issues concerning the architecture of time divided closed loop accelerometer. For this particular architecture mathematical relationship between the external acceleration detected by sensor and the voltage output of the readout circuits is deduced. Both Matlab/Simulink model and Verilog-A model for such architecture are established. Simulation results agree with the mathematical formula. Readout circuits designed to work under 50kHz with feedback duty cycle η being 60% are fabricated using 0.35μm HV CMOS process. Test results show a sensitivity of 1.518V/g.

Keywords

CMOS integrated circuits; accelerometers; capacitive sensors; microsensors; readout electronics; HV CMOS process; Matlab/Simulink model; Verilog-A model; closed loop MEMS capacitive accelerometer; external acceleration; feedback duty cycle; frequency 50 kHz; readout circuits; size 0.35 mum; time divided architecture; time divided closed loop accelerometer; voltage output; Accelerometers; Electrostatics; Force; Integrated circuit modeling; MATLAB; Mathematical model;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6466758

Filename

6466758