• DocumentCode
    598285
  • Title

    A very low specific on-resistance high-voltage SOI lateral MOSFET

  • Author

    Zhi Zheng ; Wei Li ; Hui Li ; Ping Li

  • Author_Institution
    State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China
  • fYear
    2012
  • fDate
    Oct. 29 2012-Nov. 1 2012
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    A silicon-on-insulator buried layer multiple trenches (SOI BMT) metal-oxide-semiconductor-field-effect-transistor (MOSFET) with very low specific on-resistance (Ron, sp) is proposed in this paper. Based on the research of the SOI multiple trenches MOSFET (SOI MT MOSFET) with low Ron, sp, an P-type buried layer is introduced on top of the BOX in the proposed structure, which increases the doping concentration in the N-drift region and further reduces Ron, sp. The very low Ron, sp of 6.8 mΩ·cm2 with BV of 345 V for SOI BMT MOSFET is hence obtained by 2-D simulation TCAD TOOL MEDICI. Comparing with the SOI MT MOSFET, Ron, sp is reduced by 12%, and BV is not deteriorated.
  • Keywords
    MOSFET; isolation technology; silicon-on-insulator; technology CAD (electronics); 2-D simulation TCAD TOOL MEDICI; N-drift region; P-type buried layer; SOI BMT MOSFET; doping concentration; metal-oxide-semiconductor-field-effect-transistor; silicon-on-insulator buried layer multiple trenches; very low specific on-resistance high-voltage SOI lateral MOSFET; voltage 345 V; Doping; Electric fields; Junctions; Logic gates; MOSFET circuits; Silicon; Silicon on insulator technology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
  • Conference_Location
    Xi´an
  • Print_ISBN
    978-1-4673-2474-8
  • Type

    conf

  • DOI
    10.1109/ICSICT.2012.6467589
  • Filename
    6467589