DocumentCode :
598330
Title :
A reliability model for CMOS circuit based on device degradation
Author :
Peng, Junbiao ; Huang, D.M. ; Jiao, G.F. ; Li, M.F.
Author_Institution :
Dept. of Microelectron., Fudan Univ., Shanghai, China
fYear :
2012
fDate :
Oct. 29 2012-Nov. 1 2012
Firstpage :
1
Lastpage :
3
Abstract :
CMOS device degradations such as negative bias temperature instability (NBTI) and hot carrier injection (HCI) have been extensively investigated. However, the relationship between the device degradation and the circuit reliability is not well established. In this paper, we propose a model for the frequency degradation of the ring oscillator (RO) after static stress based on the device degradations of NBTI. The model is demonstrated by using the SMIC 65nm technology. We found that the frequency degradation is much significant for the RO consisting of short (60 nm) channel devices as compared to that of long (130 nm) channel devices. The difference is essentially due to the HCI which dominates the degradation of the RO consisting of short channel devices. Combine the proposed model and the frequency degradation of the RO under dynamic stress, the contribution of NBTI and HCI is distinguished.
Keywords :
CMOS integrated circuits; integrated circuit reliability; oscillators; CMOS circuit; HCI; NBTI; RO; SMIC technology; circuit reliability; device degradation; dynamic stress; frequency degradation; hot carrier injection; long channel devices; negative bias temperature instability; ring oscillator; short channel devices; size 60 nm; size 65 nm; static stress; Degradation; Human computer interaction; Integrated circuit modeling; Inverters; MOSFETs; Semiconductor device modeling; Stress;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
Type :
conf
DOI :
10.1109/ICSICT.2012.6467686
Filename :
6467686
Link To Document :
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