DocumentCode
598342
Title
Potential floating layer SOI LDMOS for breakdown voltage enhancement
Author
Zhi Zheng ; Wei Li ; Ping Li
Author_Institution
State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fYear
2012
fDate
Oct. 29 2012-Nov. 1 2012
Firstpage
1
Lastpage
3
Abstract
A Potential Floating Layer Silicon-On-Insulator (PFL SOI) Lateral Double-diffused Metal-Oxide-Semiconductor (LDMOS) is proposed. In this proposed structure, the floating layer can pin the potential for modulating bulk field. The simulation results indicate that BV is increased from 317V to 603V compared to the Conventional REduced SURface Field (RESURF) SOI (CSOI) LDMOS, yielding a 90% improvement.
Keywords
MOS integrated circuits; silicon-on-insulator; voltage measurement; breakdown voltage enhancement; lateral double-diffused metal-oxide-semiconductor; potential floating layer SOI LDMOS; silicon-on-insulator; Electric breakdown; Electric fields; Electric potential; Equations; Silicon; Silicon on insulator technology; Substrates;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location
Xi´an
Print_ISBN
978-1-4673-2474-8
Type
conf
DOI
10.1109/ICSICT.2012.6467704
Filename
6467704
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