A novel baseband digital signal processor IC for HINOC

Author

Chun Yang ; Cheng Zhang ; Hanwen Sun ; Xiaoxin Cui ; Shi Zhang ; Weitao Pan ; Bing Zhang ; Zhiliang Qiu ; Hongbin Li

Author_Institution

State Key Lab. on Adv. Opt. Commun. Syst. & Networks, Peking Univ., Beijing, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

A novel high-performance baseband digital signal processor IC for High Performance Network Over Coax (HINOC) is implemented in this paper. The design has been fabricated with SMIC CMOS 0.13um 1P8M technology. The chip die size is 10.5 mm × 10.5 mm, in which HIPHY (HINOC Physical layer) transceiver and HIMAC (HINOC Media Access Control layer) acceleration coprocessor are integrated. Using a channel bandwidth of 16 MHz, the peak Ethernet data throughput is 76 Mbps for downstream or upstream within 36 dB link attenuation. No evident performance degradation is found when handling the short Ethernet packets compared with the long ones.

Keywords

CMOS digital integrated circuits; access protocols; coprocessors; digital signal processing chips; integrated circuit design; local area networks; transceivers; HIMAC acceleration coprocessor; HINOC media access control layer; HINOC physical layer; HIPHY transceiver; SMIC CMOS 1P8M technology fabrication; bandwidth 16 MHz; bit rate 76 Mbit/s; channel bandwidth; chip die size; high performance network over coax; high-performance baseband digital signal processor IC; link attenuation; peak Ethernet data throughput; performance degradation; short Ethernet packets; size 0.13 mum; Acceleration; Attenuation; Baseband; Coprocessors; Throughput; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6467710

Filename

6467710