DocumentCode
598346
Title
A 40-Gb/s low-power wireline transceiver architecture with multi-phase injection-locked clocking scheme
Author
Wei-Xin Gai ; Te Han
Author_Institution
Dept. of Microelectron., Peking Univ., Beijing, China
fYear
2012
fDate
Oct. 29 2012-Nov. 1 2012
Firstpage
1
Lastpage
4
Abstract
A low-power transceiver architecture that employs multi-phase injection-locked clocking scheme is presented. The minimal power consumption is realized by reducing global clock frequency and using the interleaving/multi-phase techniques. Besides, injection-locked clocking is utilized to prevent the degradation of transceiver jitter performance. In a 65-nm CMOS process, the proposed 40-Gb/s transceiver consumes 170 mW and achieves the power efficiency of 4.25 mW/Gb/s.
Keywords
CMOS integrated circuits; jitter; low-power electronics; radio transceivers; CMOS process; bit rate 40 Gbit/s; global clock frequency; interleaving technique; low-power wireline transceiver architecture; multiphase injection-locked clocking scheme; power 170 mW; power consumption; power efficiency; size 65 nm; transceiver jitter; CMOS integrated circuits; Clocks; Jitter; Phase locked loops; Phase noise; Power demand; Transceivers;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location
Xi´an
Print_ISBN
978-1-4673-2474-8
Type
conf
DOI
10.1109/ICSICT.2012.6467711
Filename
6467711
Link To Document