A low power 45-dB DR all-digital assisted AGC loop for a GNSS receiver in 0.18 um CMOS

A low-power all-digital assisted automatic gain control (AGC) loop for a GNSS receiver is presented. Single AGC loop in one I/Q path is composed of three-stage programmable gain amplifier (PGA), a 4-bit ADC and an all-digital AGC. Besides being controlled by an AGC loop, the gain of the PGAs could be alternatively controlled by an off-chip digital baseband processor through the SPI interface. To obtain low power consumption we make the PGAs be flexible and the AGC all-digital designed. The source degenerated structure is adopted in the 2^nd stage of the PGAs to achieve high linearity. Implemented in 180 nm CMOS, the simulated PGA total gain ranges from 5.08 to 49.74 dB with maximum step error 0.06 dB when working at the low power mode. When working at this mode the simulated attenuation of the PGAs at 15 MHz is less than 0.4 dB and the total NF of the PGAs is 29.92 dB. The single AGC loop consumes less than 1.4 mA current from a 1.7V supply at the low power mode and 2.1 mA at the high power mode.