DocumentCode
598373
Title
Latchup I/O to I/O adjacency issues in peripheral I/O design for digital and analog applications
Author
Voldman, S.H.
Author_Institution
Dr. Steven H. Voldman LLC, South Burlington, VT, USA
fYear
2012
fDate
Oct. 29 2012-Nov. 1 2012
Firstpage
1
Lastpage
3
Abstract
CMOS latchup is a concern of standard cells in digital and analog design for peripheral I/O implementations. In this paper, I/O to I/O latchup analysis will be discussed. Test structures, and experimental results of I/O to I/O design issues will be shown. Interesting experimental effects have been observed and will be discussed for the first time.
Keywords
CMOS integrated circuits; integrated circuit design; CMOS latchup; I/O to I/O latchup analysis; latchup adjacency; peripheral I/O design; test structures; BiCMOS integrated circuits; CMOS integrated circuits; CMOS technology; Capacitors; MOSFETs; Standards; Substrates;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location
Xi´an
Print_ISBN
978-1-4673-2474-8
Type
conf
DOI
10.1109/ICSICT.2012.6467755
Filename
6467755
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