Cu/Airgap integration on 90nm Cu BEOL process platform

As IC technology continues scaling, the performance of IC chip is no longer limited to the transistor level, but the RC delays associated with the metal interconnects. To improve performance of interconnects, Cu/low-k structure was introduced to reduce the parasitic resistance and capacitance in advanced CMOS technology. But when CMOS technology is scaling down to 16nm and beyond, Cu BEOL extension technology need to be developed to meet the chip performance requirements. According to ITRS 2011, Cu/Airgap integration is the most promising Cu-Extension technology, as airgap is the ultimate low-k material in microelectronics and air has a lowest dielectric constant close to 1.0. These are many different Cu/Airgap integration schemes, such as CVD non-conformal filling and sacrificial layer, etc, and most of which need additional and complicated process. In this work, a sample scheme was introduced in which airgap was formed by IMD etchback and optimized CVD filling process. During the etchback process, Cu line was used as hardmask to remove the IMD material with power and plasma density well controlled to reduce the influence to FEOL device. Optimized CVD dielectric filling process was developed to form Cu/Airgap structure with planarization consideration. All the work was done on 90nm Cu BEOL process platform with metal1 minimum line/space = 120nm/120nm. From the experimental results, Cu/airgap structure was formed with airgap sealed just below Cu line surface, and there is no obviously resistance increasing compared with baseline process.