Title :
Multi-level reliability simulation for IC design
Author :
Sutaria, Ketul ; Velamala, Jyothi ; Yu Cao
Author_Institution :
Sch. of Electr., Comput. & Energy Eng., Arizona State Univ., Tempe, AZ, USA
fDate :
Oct. 29 2012-Nov. 1 2012
Abstract :
CMOS IC design is challenged by the ever-increasing reliability issues, demanding highly accurate and efficient reliability simulation methodology. This paper presents multi-level solutions for reliability prediction in digital and analog design, including (1) device-level long-term aging models that capture unique operation patterns in digital and analog design, (2) circuit-level simulation method for analog reliability analysis, and (3) gate-level reliability simulation for large-scale digital designs. These solutions are integrated into IC design tools, helping diagnose critical conditions for circuit failure and enable adaptive design for resilience.
Keywords :
CMOS integrated circuits; analogue integrated circuits; circuit simulation; integrated circuit design; integrated circuit modelling; integrated circuit reliability; CMOS IC design; IC design tool; adaptive design; analog design; analog reliability analysis; circuit failure; circuit-level simulation; device-level long-term aging model; gate-level reliability simulation; large-scale digital design; multilevel reliability simulation; reliability prediction; Aging; Analytical models; Integrated circuit modeling; Logic gates; Reliability engineering; Solid modeling;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
DOI :
10.1109/ICSICT.2012.6467818
