Title :
A Phase Lead Compensation block for DC-DC converters in PMU
Author :
Jing Gong ; Pengfei Liao ; Ping Luo ; Shaowei Zhen ; Yu Zeng
Author_Institution :
State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fDate :
Oct. 29 2012-Nov. 1 2012
Abstract :
A novel Phase Lead Compensation (PLC) for DC-DC converters in Power Management Unit (PMU) is presented in this paper. Capacitor multiplier technique and the input differential pair are implemented. With this PLC, a compact-size buck converter with a high negative Power Supply Ratio Rejection (PSRR-) is achieved. The converter is simulated in a 0.13μm CMOS process. Simulation results show the PSRR- has increased by 75db compared to conventional PLC converter, and the phase margin can reach 60° with smaller passive components (C=3.7pf, R=600k).
Keywords :
CMOS integrated circuits; DC-DC power convertors; load regulation; CMOS process; DC-DC converters; PLC converter; PMU; PSRR; buck converter; capacitor multiplier technique; differential pair; phase lead compensation; phase margin; power management unit; power supply ratio rejection; size 0.13 mum; CMOS process; Capacitance; Capacitors; Crosstalk; Phasor measurement units; Simulation; System-on-a-chip;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
DOI :
10.1109/ICSICT.2012.6467871
