Title :
A low input offset voltage input stage with base current traced compensation technique
Author :
Huang Xiaozong ; Shi Jiangang ; Liu Lintao ; Huang Wengang ; Yan Kaihua
Author_Institution :
Analog IC Design Center, SISC, Chongqing, China
fDate :
Oct. 29 2012-Nov. 1 2012
Abstract :
An input stage using Darlington configuration with a lateral PNP and a vertical PNP combination for operational amplifier (Op-Amp) is presented in this paper. The emitter degeneration resistors are added to enhance the slew rate of the amplifier. To decrease the input offset voltage, the base current traced compensation technique is used to balance and compensate the different current component between the two input current branches through the current mirrors. This input stage is fabricated with the standard bipolar process, and the typical input offset voltage of 1mV, temperature coefficient of input offset voltage is around 5μV/°C over -55°C to 125°C, slew rate of 9.2V/μs and low input bias current are achieved without any trimming techniques.
Keywords :
current mirrors; operational amplifiers; resistors; Darlington configuration; base current traced compensation technique; current mirrors; emitter degeneration resistors; low input offset voltage input stage; op-amp; operational amplifier; standard bipolar process; trimming techniques; typical input offset voltage; vertical PNP combination; Bipolar transistors; Mirrors; Temperature distribution; Temperature measurement; Transistors; Voltage measurement;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
DOI :
10.1109/ICSICT.2012.6467873
