Title :
Evaluation of buffer organizations for network-on-chip
Author :
Ming´e Jing ; Pengshuai Ren ; Weichao Zhou ; Zhiyi Yu ; Xiaoyang Zeng
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
fDate :
Oct. 29 2012-Nov. 1 2012
Abstract :
Network-on-chip (NoC) is becoming increasingly important in designing a system with a large number of modules. Among many important issues, buffer organization of router is one of the most critical issues since it determines the area of the routers, and also affects the system performance significantly. In this paper, we evaluate and compare the NoC performance for several different allocations of virtual channels and channel buffer sizes under fixed buffer resources, to guide the design of buffer organization. The experiment results reveal that moderate number of virtual channels is optimal.
Keywords :
buffer circuits; network routing; network-on-chip; NoC performance; buffer organization evaluation; channel buffer size; network-on-chip; router; virtual channels; Computational modeling; Computer architecture; Organizations; Resource management; Switches; Throughput; Traffic control; Buffer size; Latency; Network-on-chip (NoC); Packet size; Throughput; Virtual channel;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
DOI :
10.1109/ICSICT.2012.6467882
