Title :
13 GHz programmable frequency divider in 65 nm CMOS
Author :
Jian Kang ; Peng Qin ; Xiaoyong Li ; Tingting Mo
Author_Institution :
Sch. of Microelectron., Center for Analog/RF Integrated Circuits (CARFIC), Shanghai Jiao Tong Univ., Shanghai, China
fDate :
Oct. 29 2012-Nov. 1 2012
Abstract :
This paper presents a CMOS high speed frequency divider which can operate at up to 13GHz. The divider core is composed of a divide by 8/9 dual modulus prescaler and a programmable digital counter. The divide by 8/9 dual modulus prescaler is realized by CML structure which operates around 6GHz. The digital counter is composed of logic gates and TSPC D flip-flops which operate at around 700MHz. The total division ratio is programmable and controlled by the input to the digital counter. The proposed frequency divider is designed and simulated in a 65 nm CMOS process and is capable of working robustly over the process, voltage supply, and temperature (P.V.T) variations.
Keywords :
CMOS integrated circuits; counting circuits; frequency dividers; logic gates; 8-9 dual modulus prescaler; CMOS high speed frequency divider; TSPC D flip-flops; divider core; frequency 13 GHz; logic gates; programmable digital counter; programmable frequency divider; size 65 nm; temperature variations; voltage supply; CMOS integrated circuits; Delay; Flip-flops; Frequency conversion; Logic gates; Propagation delay; Radiation detectors;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
DOI :
10.1109/ICSICT.2012.6467883
