Title :
A high PVT tolerance TDC with symmetrical Vernier delay ring
Author :
Biao Zhou ; Yajuan He ; Ping Luo
Author_Institution :
State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fDate :
Oct. 29 2012-Nov. 1 2012
Abstract :
A novel Vernier delay ring (VDR) used in time-to-digital converter (TDC) is presented in this paper. This Vernier delay ring is perfectly symmetrical compared with traditional Vernier ring by introducing a set of buffers and loads. It significantly reduces the affects of circuit parameters on the process, supply voltage and temperature (PVT) variations. This circuit also inherits the merits of the traditional Vernier ring time-to-digital converter (VRTDC), such as high resolution, large detectable rang. The proposed Vernier Delay Ring TDC achieves a 0.004ps/°C temperature coefficient of time resolution in 0.13μm CMOS technology.
Keywords :
CMOS integrated circuits; time-digital conversion; CMOS technology; VDR; buffers; circuit parameters; high PVT tolerance TDC; loads; process supply voltage and temperature variations; size 0.13 mum; symmetrical Vernier delay ring; time resolution; time-to-digital converter; Delay; Inverters; Laser stability; Layout; Quantization; Radiation detectors; Signal resolution;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
DOI :
10.1109/ICSICT.2012.6467894
