DocumentCode
598452
Title
A SHA-less 10-bit 80-MS/s CMOS pipelined ADC
Author
Young-Mok Jung ; Jin Zhe ; Chan-Keun Kwon ; Hoon-Ki Kim ; Soo-won Kim
Author_Institution
Dept. of Electr. Eng., Korea Univ., Seoul, South Korea
fYear
2012
fDate
Oct. 29 2012-Nov. 1 2012
Firstpage
1
Lastpage
3
Abstract
This paper describes a 10-bit, 80MS/s CMOS pipelined Analog to Digital converter(ADC) that is implemented in a standard 180 nm technology. The ADC removes the Sample-and-Hold amplifier (SHA) to save power dissipation and die chip area. A 1.5 bit/stage architecture is used in the first stage to lower front-end. The pipelined ADC achieved a peak signal-to-noise-and-distortion ratio(SNR) of 58.2 dB, and a power consumption of 55 mW.
Keywords
CMOS analogue integrated circuits; amplifiers; analogue-digital conversion; sample and hold circuits; CMOS pipelined ADC; CMOS pipelined analog to digital converter; SHA; SNR; aample-and-hold amplifier; die chip area; noise figure 58.2 dB; peak signal-to-noise-and-distortion ratio; power 55 mW; power consumption; power dissipation; size 180 nm; word length 10 bit; CMOS integrated circuits; CMOS technology; Clocks; Gain; Pipelines; Power dissipation; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location
Xi´an
Print_ISBN
978-1-4673-2474-8
Type
conf
DOI
10.1109/ICSICT.2012.6467927
Filename
6467927
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