System development of high-performance, low-cost 1333Mbps LPDDR2 memory interface

A system level development methodology of high performance, low cost LPDDR2 memory interface including Chip-PKG-PCB co-design, Chip-PKG-PCB co-simulation, system verification, and waveform correlation was introduced. Specifically, Chip-PKG-PCB co-design flow makes it possible to further optimize the system performance in a restricted environment. Chip-PKG-PCB co-simulation helps us evaluating the system performance and figuring out the system bottleneck. System verification and correlation are also necessary to reduce the deviation from the simulation and real situation. All these three steps are essential in developing a high performance, low-cost memory interface. In this paper, a low-cost side-by-side LPDDR2 memory system was successfully designed and implemented in 4-layer flip-chip substrate and 6-layer HDI-1 PCB with data speed up to 1333Mbps.