Design of sample and hold merged with 2.5 bit multiplying digital-to-analog converter

A design of a SHA merged with MDAC(SMDAC) which can be used in a 14 bit 80Msps pipelined analog-to-digital converter (ADC) is presented in this paper. A two-stage transconductance-controlled op-amp is used in the SMDAC to ensure the requirment of the resolution, speed and stability of the circuit when its feedback factor alternate between 1/2 and 1/4. Simulation by cadence based on Chartered 0.18µ 1P5M CMOS process under 1.8V supply voltage shows 116dB loop gain, 1.05GHz unity gain bandwidth and 61° phase margin in two different feedback factors of the op-amp. The output signal of the S/H phase and MDAC phase can be settled to 14bit and 12bit accuracy in 5ns, respectively.