Sampled analog VLSI architecture to implement discrete Daubechies wavelet transform

A real-time sampled analog VLSI architecture is designed to implement discrete Daubechies wavelet transform (DDWT). This architecture process discrete time continuous level samples that avoids the requirement of complex data converters, where as in digital architectures these data converters are necessary to generate digital samples that consumes extra power and silicon area usage. Characterized by the absence of the quantization process and thus of the data converters this architecture gives good price-performance ratio compared to their digital implementations. Discrete time switched capacitor integrator circuit, based on gain-boosted folded cascode operational amplifier, serves as the building block for the proposed architecture. This architecture is designed in 0.18µm CMOS process and corresponding simulation results are presented.