Design of synchronous sequential circuits with low standby sub-threshold leakage-power using back gate bias and testability logic

The paper proposes a scheme to reduce the leakage(sub-threshold) standby power in synchronous sequential circuits by using back gate bias, scannable flip-flops and control point insertion. A back gate bias can be applied to the combinational circuit during standby mode for low leakage. Scan Design is the most widely used structured DFT methodology, attempts to improve testability of a circuit by improving controllability and observability of storage elements in a sequential design. These scannable latches will be used to regain the state and output combination in which we want the circuit to be in after standby period is over.