DocumentCode :
5991
Title :
Multistrata Subsurface Laser-Modified Microstructure With Backgrind-Assisted Controlled Fracture for Defect-Free Ultrathin Die Fabrication
Author :
Weng Hong Teh ; Boning, Duane S. ; Welsch, Roy E.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA
Volume :
5
Issue :
7
fYear :
2015
fDate :
Jul-15
Firstpage :
1006
Lastpage :
1018
Abstract :
We report the development of multistrata subsurface IR (1.342 μm) nanosecond pulsed laser die singulation [stealth dicing (SD)] on high backside reflectance (up to 82%) Si wafers. We study the microstructural properties and formation mechanisms of the subsurface Si dislocation belt layer with respect to laser scanning speed, pulse laser energies, and interstrata distances. We optimize and exploit the multistrata interactions between generated thermal shock waves and the preceding dislocation belt layers formed to initiate frontal crack fractures that separate out the individual dies from within the interior of the wafer. A new partial-SD before grinding (p-SDBG) integration scheme based upon the tandem use of three-strata SD for controlled crack fracture toward the frontside of the wafer followed by static loading from backgrinding to complete full kerf separation is demonstrated. The optimized three-strata SD process and p-SDBG integration scheme can be used to compensate for the high backside reflectance wafers to produce defect-free eight die stacks of 25-μm-thick mechanically functional and 46-μm-thick electrically functional 2-D NAND memory dies.
Keywords :
elemental semiconductors; integrated circuit manufacture; integrated circuit technology; pulsed laser deposition; silicon; NAND memory dies; Si; Si wafers; backgrind-assisted controlled fracture; backside reflectance; defect-free ultrathin die fabrication; kerf separation; laser scanning; multistrata subsurface IR nanosecond pulsed laser die singulation; multistrata subsurface laser-modified microstructure; p-SDBG integration scheme; partial-SD before grinding integration scheme; pulse laser energy; reflectance wafers; size 1.342 mum; size 25 mum; size 46 mum; stealth dicing; thermal shock waves; Laser transitions; Measurement by laser beam; Monitoring; Power lasers; Shock waves; Silicon; Defects; laser; semiconductor device manufacture; semiconductor device packaging; semiconductor memory; wafer dicing; wafer dicing.;
fLanguage :
English
Journal_Title :
Components, Packaging and Manufacturing Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
2156-3950
Type :
jour
DOI :
10.1109/TCPMT.2015.2435369
Filename :
7151828
Link To Document :
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