Stochastic hardware architectures: A survey

Many emerging computer applications may be classified into recognition, mining, and synthesis (RMS) applications, or into stream-based media applications. One interesting and useful property of such applications is that they are tolerant to errors. In fact, these applications allow discrepancies in intermediate computations, but nevertheless are able to provide “acceptable” results. Research in this area leveraged this error tolerance in order to relax the zero-error tolerance requirement at the hardware level, and to shift error correction or concealment to the software application level. The main advantage of using such stochastic hardware architectures is in the major energy savings that are obtained since the circuits can be operated at reduced power supply levels. The hardware errors may be due to different components in the computer system. The purpose of this paper is to conduct a survey on techniques used in the design of stochastic architectures.