A fast hardware/software co-verification method using a real hardware acceleration

Due to the number and the nature of components integrated in them, Systems-On-a-Chip (SoC) have become increasingly complex. To solve the problem of cost, flexibility and the time-to-market, systems designed with mixed hardware software systems has increased and the verification method has become a key position of the design process. This paper describes a new hardware/software co-verification methodology for SoC, based on the integration of a SystemC simulator and an FPGA accelerator. Between the SystemC simulator [1] [2] and the FPGA board, a shared communication was established to accelerate the simulation via flexible interfaces. The key issue is the synchronization between the two parts.