Fault injection for verifying testability of fault tolerant structures at the Verilog level

An integrated circuit is said efficient if it is able to perform its intended function with a level of quality and reliability of the highest. To ensure the quality of operation, it is necessary to test and verify these circuits in the early steps of design. This article aims to present a specific test procedure, in order to alleviate the problem of testing the fault-tolerant of structures by minimizing the cost associated with it.