Study and modeling of defects in integrated circuits for their reliability analysis

Nanometric technologie is the way for the realization of numerical structures of considerable size gathering several hundreds of million transistors on one chip. This miniaturization makes manufacturing processes more complex and less reliable. By consequence, the output of manufacture is likely to drop considerably. To improve the output, the first thing is the optimization of the manufactoring processes. On the other hand, when the latter reach their limits, it will be necessary to find a solution on the level of the design. The faults tolerance techniques can be the solution to these problems. However, the higher expectation of reliability can only be met by more thorough and comprehensive testing of this structure. This paper analyzes the ability of these structures to tolerate manufacturing defects and the conditions to improve the yield and therefore their reliability.