TSV impact on circuit performance and recommended design methodologies

In this paper, a lumped element model for a through silicon via (TSV) is proposed based on the TSV physics. The proposed model is compact and compatible with SPICE simulators, hence it allows fast investigation of the TSV impact on 3-D circuits´ performance. Exploiting this attractive feature of the proposed model, it is shown that the TSV has a negligible effect on high-impedance device characteristics, and in such cases the TSV can be modeled a capacitance-dominated structure. In contrary, in case of low-impedance devices, the TSV has a significant effect on the device characteristics and the full TSV model need to be used. Moreover, this paper shows that the capacitive coupling between TSVs is significant and larger than the self capacitance while the inductive coupling is small and can be neglected. Some design methodologies are also presented here for signal integrity (SI), power integrity (PI), and thermal integrity (TI).