Sidewall roughness control in deep reactive ion etch process for micromachined Si devices

An approach for controlling sidewall smoothness through deep reactive ion etch (DRIE) was developed for silicon micro-optical applications. The process relies on carefully controlled over-passivation of the etched sidewall during the etch/passivation cycles of the advanced Si etch (ASE) process. Several parameters of the ASE process such as etch/passivation cycle time, coil power, platen power, and etching gas flow were systematically varied to achieve an optimized process recipe. The rms roughness of the sidewall after gold deposition was found to be around 3.9 nm. Our structure represents the lowest reported sidewall roughness achieved using only a DRIE process.