An elitist area-power density trade-off in VLSI floorplan using genetic algorithm

Due to trade-offs between the VLSI circuit parameters, chip suffers from reliability issues. It needs to be optimizing for better performance. Such problems are defined as NP-hard problems. In this paper a heuristic has been developed using genetic algorithm for solving the floorplan problem. The proposed algorithm is an improved floorplan algorithm, for optimizing simultaneously the trade-off parameters area and zonal peak power density. The initial populations are randomly chosen from a superset of large initial population & genetic algorithm is implemented to obtain the best floorplan solution. Randomized selection is taken to make the selection area flexible. The proposed algorithm has been validated with the ISCAS85 benchmark circuits for 65nm and 90nm.